--------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Copyright (C) 2004 Free Model Foundry; http://www.FreeModelFoundry.com/ -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- --------------------------------------------------------------------------- -- -- Company : HDL Design House, Serbia and Montenegro -- Project : PSPP1284 -- Module : i2c_drive_ms_pkg -- -- Date : 12.03.2004 -- Ver. : 1.0 -- -- Author : J.Bogosavljevic -- Email : j-bogosavljevic@hdl-dh.com -- Phone : +381 11 344 23 59 -- -- Customer : -- --------------------------------------------------------------------------- -- -- Functional description of the module: -- i2c_drive_ms_pkg generates commands that drive i2c masters and -- slaves. Used to simulate devices connected to i2c bus over i2c bus -- interface -- ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE STD.textio.ALL; LIBRARY FMF; USE FMF.gen_utils.all; USE FMF.conversions.all; ------------------------------------------------------------------------------- -- ENTITY DECLARATION ------------------------------------------------------------------------------- PACKAGE i2c_drive_ms_pkg IS --------------------------------------------------------------------------- --TC type --------------------------------------------------------------------------- TYPE TC_type IS RECORD SERIES : NATURAL RANGE 1 TO 30; TESTCASE : NATURAL RANGE 1 TO 15; END RECORD; --------------------------------------------------------------------------- -- commands to the device --------------------------------------------------------------------------- TYPE CMD_TYPE IS ( done, idle, none, req_bus, write, read, delay_clk, dis_sl_resp ); --------------------------------------------------------------------------- -- --------------------------------------------------------------------------- TYPE cmd_rec IS RECORD device_id : STRING(11 downto 1); cmd : cmd_type; wr_byte : NATURAL; rd_byte_num : NATURAL ; wtime : time; --valid with wt cmd END RECORD; --number of testcases pre testseriese TYPE tc_list IS ARRAY (1 TO 30) OF NATURAL; CONSTANT tc : tc_list := --0 1 2 3 --1-2-3-4-5-6-7-8-9-0-1-2-3-4-5-6-7-8-9-0-1-2-3-4-5-6-7-8-9-0 (1,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9); --TC command sequence TYPE cmd_seq_type IS ARRAY(0 TO 200) OF cmd_rec; SHARED VARIABLE t :TIME := 200 us; --------------------------------------------------------------------------- --PUBLIC --PROCEDURE to generate command sequence --------------------------------------------------------------------------- PROCEDURE Generate_TC ( Device_id : IN STRING ; Series : IN NATURAL RANGE 1 TO 30; TestCase : IN NATURAL RANGE 1 TO 30; curr_time : IN TIME; command_seq : OUT cmd_seq_type ); END PACKAGE i2c_drive_ms_pkg; PACKAGE BODY i2c_drive_ms_pkg IS --------------------------------------------------------------------------- --Public PROCEDURE to generate command sequence --------------------------------------------------------------------------- PROCEDURE Generate_TC ( device_id : IN STRING ; Series : IN NATURAL RANGE 1 TO 30; TestCase : IN NATURAL RANGE 1 TO 30; curr_time : IN TIME; command_seq : OUT cmd_seq_type ) IS VARIABLE len : NATURAL := 11; VARIABLE all_dev : STRING(len downto 1); VARIABLE dev0 : STRING(len downto 1) := "U00_i2c_dev"; VARIABLE dev1 : STRING(len downto 1) := "U01_i2c_dev"; VARIABLE dev2 : STRING(len downto 1) := "U02_i2c_dev"; -- hardware masters VARIABLE dev20 : STRING(len downto 1) := "U20_i2c_dev"; VARIABLE dev21 : STRING(len downto 1) := "U21_i2c_dev"; VARIABLE dev22 : STRING(len downto 1) := "U22_i2c_dev"; VARIABLE dev23 : STRING(len downto 1) := "U23_i2c_dev"; -- 7 bit addressing VARIABLE slv0_r : NATURAL := 2#0101_0101#; VARIABLE slv0_w : NATURAL := 2#0101_0100#; VARIABLE slv1_r : NATURAL := 2#0101_0001#;--2#0101_0111#; VARIABLE slv1_w : NATURAL := 2#0101_0000#;--2#0101_0110#; -- 10 bit addressing VARIABLE slv2 : NATURAL := 2#1010_1000#;--11 "11_1010_1000" VARIABLE slv3 : NATURAL := 2#1010_1000#;--10 "10_1010_1000" -- hardware master VARIABLE slv22 : NATURAL := 2#0010_0010#;--22 "11_0010_0010" -- hardware masters VARIABLE slv20_r : NATURAL := 2#0101_0111#; -- hardware master that is in slave receive mode after system reset VARIABLE slv21_w : NATURAL := 2#0101_1000#; VARIABLE slv21_r : NATURAL := 2#0101_1001#; -- no slave should have this address VARIABLE no_slv_r : NATURAL := 2#1110_0001#; VARIABLE no_slv_w : NATURAL := 2#1110_0000#; -- general call VARIABLE gen_call : NATURAL := 2#0000_0000#; VARIABLE start : NATURAL := 2#0000_0001#; VARIABLE t : TIME := 200 us; VARIABLE t_curr : TIME := 0 ns; BEGIN t := curr_time + t; t_curr := curr_time; FOR i IN 1 TO 200 LOOP --device_id, cmd, wr_byte, rd_byte_num ,wtime command_seq(i) :=(all_dev,done,0,0,0 ns); END LOOP; all_dev(7 downto 1) := "all_dev"; IF device_id = dev0 THEN REPORT "------------------------------------------------------" ; REPORT "------------------------------------------------------" ; REPORT "TestSeries : "& to_int_str(Series )&" "& "TC : "& to_int_str(TestCase); REPORT "------------------------------------------------------" ; END IF; CASE Series IS WHEN 1 => -- POWER UP, bus is free REPORT "Power up, bus is free"; --device_id, cmd, wr_byte, rd_byte_num ,wtime command_seq(1) :=(all_dev ,idle ,0,0,t); command_seq(2) :=(all_dev ,done ,0,0,0 ns); ------------------------------------------------ -- HARDWARE MASTER TEST SERIES -- GENERAL CALL -- TSs 2-6 ------------------------------------------------ WHEN 2 => -- NEGATIVE HARDWARE MASTER CAN NOT BE READ CASE Testcase IS WHEN 1 => REPORT "Negative, hardware master can not be read"; -- read request to hw master 20; hw master is not slave command_seq(1) :=(dev0 ,req_bus ,slv20_r,0,0 ns); -- read request to hw master 21; hw master is slave command_seq(2) :=(dev0 ,req_bus ,slv21_r,0,0 ns); -- read request to hw master 22; hw master 10bit addr, is slave command_seq(3) :=(dev0 ,req_bus ,2#1111_0110#,0,0 ns); command_seq(4) :=(dev0 ,write ,slv22,0,0 ns); command_seq(5) :=(dev0 ,req_bus ,2#1111_0111#,0,0 ns); command_seq(6) :=(all_dev ,idle ,0,0,t+600 us); command_seq(7) :=(all_dev ,done ,0,0,0 ns); WHEN OTHERS => NULL; END CASE; WHEN 3 => -- SETTING ADDRESS DATA WILL BE SENT TO -- (DUMP ADDRESS) FOR HARDWARE MASTER THAT -- IS IN SLAVE RECEIVE MODE AFTER SYSTEM RESET CASE Testcase IS WHEN 1 => -- hardware master (7bit address) -- program dump address (address hardware master will send data to) REPORT "Set dump address, hw master has 7 bit address, "& "master writes dump address to hw master(slave)"; command_seq(1) :=(dev0 ,req_bus ,slv21_w,0,0 ns); -- dump adress is slave2 address command_seq(2) :=(dev0 ,write ,slv1_w,0,0 ns); command_seq(3) :=(all_dev ,idle ,0,0,t); command_seq(4) :=(all_dev ,done ,0,0,0 ns); WHEN 2 => -- hardware master (10bit address) -- program dump address (address hardware master will send data to) REPORT "Set dump address, hw master has 10 bit address, "& "master writes dump address to hw master(slave)"; -- slv22 has 10 bit addr command_seq(1) :=(dev0 ,req_bus ,2#1111_0110#,0,0 ns); command_seq(2) :=(dev0 ,write ,slv22,0,0 ns); -- write dump address command_seq(3) :=(dev0 ,write ,slv1_w,0,0 ns); command_seq(4) :=(all_dev ,idle ,0,0,t+200 us); command_seq(5):=(all_dev ,done ,0,0,0 ns); --WHEN 3 => see TC4.1 dev23 -- set dump address using general call procedure --WHEN 3 => --set dump address in HS mode (7 bit addressing) --WHEN 4 => --set dump address in HS mode (10 bit addressing) WHEN OTHERS => NULL; END CASE; ------------------------------------------------ -- GENERAL CALL -- TSs 4-5 ------------------------------------------------ WHEN 4 => -- GENERAL CALL PORCEDURE TO SLAVES CASE Testcase IS WHEN 1 => REPORT "General call procedure, second byte is 0x04"; command_seq(1) :=(dev0 ,req_bus ,gen_call,0,0 ns); command_seq(2) :=(dev0 ,write ,16#04#,0,0 ns); command_seq(3) :=(all_dev ,idle ,0,0,t+200 us); command_seq(4) :=(all_dev ,done ,0,0,0 ns); WHEN 2 => REPORT "General call procedure, second byte is 0x06"; command_seq(1) :=(dev0 ,req_bus ,gen_call,0,0 ns); command_seq(2) :=(dev0 ,write ,16#06#,0,0 ns); command_seq(3) :=(all_dev ,idle ,0,0,t+200 us); command_seq(4) :=(all_dev ,done ,0,0,0 ns); WHEN 3 => REPORT "New transaction after GENERAL CALL procedure"; command_seq(1) :=(dev0 ,req_bus ,gen_call,0,0 ns); command_seq(2) :=(dev0 ,write ,16#06#,0,0 ns); command_seq(3) :=(dev0 ,req_bus ,slv1_w,0,0 ns); command_seq(4) :=(dev0 ,write ,16#06#,0,0 ns); command_seq(5) :=(all_dev ,idle ,0,0,t+400 us); command_seq(6) :=(all_dev ,done ,0,0,0 ns); WHEN OTHERS => null; END CASE; WHEN 5 => -- GENERAL CALL PROCEDURE FROM HARDWARE MASTER CASE Testcase IS -- byte_to_write field is ignored in req_bus and first write commands, -- it is always set "00000000" and hardware address -- in model when hardware master requests bus WHEN 1 => REPORT "General call procedure from hw master device20, master terminates write"; -- dev20 is hardware master, dev0 should listen to it command_seq(1) :=(dev20 ,req_bus ,16#01#,0,0 ns);-- gen_call command_seq(2) :=(dev20 ,write ,16#00#,0,0 ns);-- slv20_r -- byte_to_write field is not ignored any more command_seq(3) :=(dev20 ,write ,16#06#,0,0 ns); command_seq(4) :=(dev20 ,write ,16#07#,0,0 ns); command_seq(5) :=(dev20 ,write ,16#08#,0,0 ns); command_seq(6) :=(all_dev ,idle ,0,0,t+400 us); command_seq(7) :=(all_dev ,done ,0,0,0 ns); WHEN 2 => -- hardware master dev20 REPORT "General call procedure from hw master device20, slave terminates write"; command_seq(1) :=(dev20 ,req_bus ,gen_call,0,0 ns); command_seq(2) :=(dev20 ,write ,slv20_r,0,0 ns); -- byte_to_write field is not ignored any more command_seq(3) :=(dev20 ,write ,16#09#,0,0 ns); command_seq(4) :=(dev20 ,write ,16#0A#,0,0 ns); command_seq(5) :=(dev1 ,idle ,0,0,t+100 us); command_seq(6) :=(dev1 ,dis_sl_resp ,0,0,50 us); command_seq(7) :=(all_dev ,idle ,0,0,t+400 us); command_seq(8) :=(all_dev ,done ,0,0,0 ns); WHEN 3 => REPORT "General call procedure from hw master device21, master terminates write"; -- general call procedure hw master dev21 command_seq(1) :=(dev21 ,req_bus ,16#00#,0,0 ns); command_seq(2) :=(dev21 ,write ,16#00#,0,0 ns); -- sends data to dev1 command_seq(3) :=(dev21 ,write ,16#11#,0,0 ns); command_seq(4) :=(dev21 ,write ,16#12#,0,0 ns); command_seq(5) :=(dev21 ,write ,16#13#,0,0 ns); command_seq(6) :=(all_dev ,idle ,0,0,t+400 us); command_seq(7) :=(all_dev ,done ,0,0,0 ns); WHEN 4 => REPORT "General call procedure from hw master device21, slave terminates write"; -- general call procedure hw master dev21 command_seq(1) :=(dev21 ,req_bus ,16#00#,0,0 ns); command_seq(2) :=(dev21 ,write ,16#00#,0,0 ns); -- sends data to dev1 command_seq(3) :=(dev21 ,write ,16#01#,0,0 ns); command_seq(4) :=(dev21 ,write ,16#14#,0,0 ns); command_seq(5) :=(dev1 ,idle ,0,0,t+100 us); command_seq(6) :=(dev1 ,dis_sl_resp ,0,0,50 us); command_seq(7) :=(all_dev ,idle ,0,0,t+400 us); command_seq(8) :=(all_dev ,done ,0,0,0 ns); WHEN 5 => REPORT "General call procedure from hw master device22, master terminates write"; -- general call procedure hw master dev22 command_seq(1) :=(dev22 ,req_bus ,16#00#,0,0 ns); command_seq(2) :=(dev22 ,write ,16#00#,0,0 ns); -- sends data to dev1 command_seq(3) :=(dev22 ,write ,16#21#,0,0 ns); command_seq(4) :=(dev22 ,write ,16#22#,0,0 ns); command_seq(5) :=(dev22 ,write ,16#23#,0,0 ns); command_seq(6) :=(all_dev ,idle ,0,0,t+400 us); command_seq(7) :=(all_dev ,done ,0,0,0 ns); WHEN 6 => REPORT "General call procedure from hw master device22, slave terminates write"; -- general call procedure hw master dev22 command_seq(1) :=(dev22 ,req_bus ,16#00#,0,0 ns); command_seq(2) :=(dev22 ,write ,16#00#,0,0 ns); -- sends data to dev1 command_seq(3) :=(dev22 ,write ,16#24#,0,0 ns); command_seq(4) :=(dev22 ,write ,16#25#,0,0 ns); command_seq(5) :=(dev1 ,idle ,0,0,t+100 us); command_seq(6) :=(dev1 ,dis_sl_resp ,0,0,50 us); command_seq(7) :=(all_dev ,idle ,0,0,t+400 us); command_seq(8) :=(all_dev ,done ,0,0,0 ns); WHEN 7 => REPORT "General call procedure from hw master device23, master terminates write"; -- general call procedure hw master dev23 command_seq(1) :=(dev23 ,req_bus ,16#00#,0,0 ns); command_seq(2) :=(dev23 ,write ,16#00#,0,0 ns); -- sends data to dev1 command_seq(3) :=(dev23 ,write ,16#31#,0,0 ns); command_seq(4) :=(dev23 ,write ,16#32#,0,0 ns); command_seq(5) :=(dev23 ,write ,16#33#,0,0 ns); command_seq(6) :=(all_dev ,idle ,0,0,t+400 us); command_seq(7) :=(all_dev ,done ,0,0,0 ns); WHEN 8 => REPORT "General call procedure from hw master device23, slave terminates write"; -- general call procedure hw master dev23 command_seq(1) :=(dev23 ,req_bus ,16#00#,0,0 ns); command_seq(2) :=(dev23 ,write ,16#00#,0,0 ns); -- sends data to dev1 command_seq(3) :=(dev23 ,write ,16#34#,0,0 ns); command_seq(4) :=(dev23 ,write ,16#35#,0,0 ns); command_seq(5) :=(dev1 ,idle ,0,0,t+100 us); command_seq(6) :=(dev1 ,dis_sl_resp ,0,0,50 us); command_seq(7) :=(all_dev ,idle ,0,0,t+400 us); command_seq(8) :=(all_dev ,done ,0,0,0 ns); WHEN OTHERS => NULL; END CASE; WHEN 6 => -- NEGATIVE AFTER HARDWARE MASTER IS INITIALIZED IT DOES NOT ACT AS SLAVE CASE Testcase IS WHEN 1 => -- hardware master (7bit address) REPORT "Negative, after hw master is initialized it can not act as a slave"; --master 21 -- old hw master slave addr command_seq(1) :=(dev0 ,req_bus ,slv21_w,0,0 ns); command_seq(2) :=(dev0 ,req_bus ,slv21_r,0,0 ns); --master 22 -- old hw master slave addr command_seq(3) :=(dev0 ,req_bus ,2#1111_0110#,0,0 ns); command_seq(4) :=(dev0 ,write ,slv22,0,0 ns); -- new hw master slave addr 21, 22, 23 command_seq(5) :=(dev0 ,req_bus ,slv1_w,0,0 ns); command_seq(6) :=(dev0 ,req_bus ,slv1_r,1,0 ns); -- general call command_seq(7) :=(dev0 ,req_bus ,gen_call,0,0 ns); -- hs mode command_seq(8) :=(all_dev ,idle ,0,0,t+700 us); command_seq(9) :=(all_dev ,done ,0,0,0 ns); WHEN OTHERS => NULL; END CASE; ---------------------------- --READ/WRITE TRANSACTIONS -- TCs 7 - 9 ---------------------------- WHEN 7 => -- INITAIAL BYTE, bus is free -- master requests bus, output initial byte -- terminates transaction after initial byte CASE Testcase IS WHEN 1 => -- master addresses itself REPORT "initial byte test, trans. write, slave response "; command_seq(1) :=(dev0 ,req_bus ,slv0_w,0,0 ns); command_seq(2) :=(all_dev ,idle ,0,0,t); command_seq(3) :=(all_dev ,done ,0,0,0 ns); WHEN 2 => -- master addresses itself REPORT "initial byte test, trans. read, slave response "; command_seq(1) :=(dev0 ,req_bus ,slv0_r,0,0 ns); command_seq(2) :=(all_dev ,idle ,0,0,t); command_seq(3) :=(all_dev ,done ,0,0,0 us); WHEN 3 => -- master addresses another slave REPORT "initial byte test, trans. write, slave response "; command_seq(1) :=(dev0 ,req_bus ,slv1_w,0,0 ns); command_seq(2) :=(all_dev ,idle ,0,0,t); command_seq(3) :=(all_dev ,done ,0,0,0 ns); WHEN 4 => -- master addresses another slave REPORT "initial byte test, trans. read, slave response "; command_seq(1) :=(dev0 ,req_bus ,slv1_r,0,0 ns); command_seq(2) :=(all_dev ,idle ,0,0,t); command_seq(3) :=(all_dev ,done ,0,0,0 us); WHEN 5 => -- master addresses non existing slave REPORT "initial byte test, trans. write, no slave response "; command_seq(1) :=(dev0 ,req_bus ,no_slv_w,0,0 ns); command_seq(2) :=(all_dev ,idle ,0,0,t); command_seq(3) :=(all_dev ,done ,0,0,0 us); WHEN 6 => -- master addresses non existing slave REPORT "initial byte test, trans. read, no slave response "; command_seq(1) :=(dev0 ,req_bus ,no_slv_r,0,0 ns); command_seq(2) :=(all_dev ,idle ,0,0,t); command_seq(3) :=(all_dev ,done ,0,0,0 us); WHEN OTHERS => null; END CASE; WHEN 8 => -- WRITE TO SLAVE, bus is free CASE Testcase IS WHEN 1 => -- master addresses itself -- master ends write REPORT "write one byte to slave test"; command_seq(1) :=(dev0 ,req_bus ,slv0_w,0,0 ns); command_seq(2) :=(dev0 ,write ,16#FF#,0,0 ns); command_seq(3) :=(all_dev ,idle ,0,0,t); command_seq(4) :=(all_dev ,done ,0,0,0 ns); WHEN 2 => -- master addresses itself -- master terminates write REPORT "write several bytes to slave test"; command_seq(1) :=(dev0 ,req_bus ,slv0_w,0,0 ns); command_seq(2) :=(dev0 ,write ,16#01#,0,0 ns); command_seq(3) :=(dev0 ,write ,16#02#,0,0 ns); command_seq(4) :=(dev0 ,write ,16#03#,0,0 ns); command_seq(5) :=(dev0 ,write ,16#55#,0,0 ns); command_seq(6) :=(dev0 ,write ,16#F0#,0,0 ns); command_seq(7) :=(all_dev ,idle ,0,0,t+500 us); command_seq(9) :=(all_dev ,done ,0,0,0 ns); WHEN 3 => -- slave "terminates write", no response REPORT "write several bytes to slave test"; command_seq(1) :=(dev0 ,req_bus ,slv0_w,0,0 ns); command_seq(2) :=(dev0 ,write ,16#AB#,0,0 ns); command_seq(3) :=(dev0 ,write ,16#22#,0,0 ns); command_seq(4) :=(dev0 ,write ,16#23#,0,0 ns); command_seq(5) :=(dev0 ,write ,16#65#,0,0 ns); command_seq(6) :=(dev0 ,dis_sl_resp ,0,0,50 us); command_seq(7) :=(all_dev ,idle ,0,0,t+400 us); command_seq(8) :=(all_dev ,done ,0,0,0 ns); WHEN 4 => -- master addresses another slave -- master ends write REPORT "write one byte to slave test"; command_seq(1) :=(dev0 ,req_bus ,slv1_w,0,0 ns); command_seq(2) :=(dev0 ,write ,16#FF#,0,0 ns); command_seq(3) :=(all_dev ,idle ,0,0,t); command_seq(4) :=(all_dev ,done ,0,0,0 ns); WHEN 5 => -- master terminates write REPORT "write several bytes to slave test"; command_seq(1) :=(dev0 ,req_bus ,slv1_w,0,0 ns); command_seq(2) :=(dev0 ,write ,16#01#,0,0 ns); command_seq(3) :=(dev0 ,write ,16#02#,0,0 ns); command_seq(4) :=(dev0 ,write ,16#03#,0,0 ns); command_seq(5) :=(dev0 ,write ,16#55#,0,0 ns); command_seq(6) :=(dev0 ,write ,16#F0#,0,0 ns); command_seq(7) :=(all_dev ,idle ,0,0,t+700 us); command_seq(9) :=(all_dev ,done ,0,0,0 ns); WHEN 6 => -- slave "terminates write", no response REPORT "write several bytes to slave test"; command_seq(1) :=(dev0 ,req_bus ,slv1_w,0,0 ns); command_seq(2) :=(dev0 ,write ,16#AB#,0,0 ns); command_seq(3) :=(dev0 ,write ,16#22#,0,0 ns); command_seq(4) :=(dev0 ,write ,16#23#,0,0 ns); command_seq(5) :=(dev1 ,idle ,0,0,t+100 us); command_seq(6) :=(dev1 ,dis_sl_resp ,0,0,50 us); command_seq(7) :=(all_dev ,idle ,0,0,t+400 us); command_seq(8) :=(all_dev ,done ,0,0,0 ns); WHEN OTHERS => NULL; END CASE; WHEN 9 => -- READ FROM SLAVE, bus is free CASE Testcase IS WHEN 1 => --master reads itslef REPORT "read one byte from slave"; command_seq(1) :=(dev0 ,req_bus ,slv0_r,0,0 ns); command_seq(2) :=(all_dev ,idle ,0,0,t); command_seq(3) :=(all_dev ,done ,0,0,0 us); WHEN 2 => REPORT "read several bytes from slave"; command_seq(1) :=(dev0 ,req_bus ,slv0_r,0,0 ns); command_seq(2) :=(dev0 ,read ,0,4,0 ns); command_seq(3) :=(all_dev ,idle ,0,0,t+300 us); command_seq(4) :=(all_dev ,done ,0,0,0 ns); WHEN 3 => --master reads from another slave REPORT "read one byte from slave"; command_seq(1) :=(dev0 ,req_bus ,slv1_r,0,0 ns); command_seq(2) :=(all_dev ,idle ,0,0,t); command_seq(3) :=(all_dev ,done ,0,0,0 us); WHEN 4 => REPORT "read several bytes from slave"; command_seq(1) :=(dev0 ,req_bus ,slv1_r,0,0 ns); command_seq(2) :=(dev0 ,read ,0,4,0 ns); command_seq(3) :=(all_dev ,idle ,0,0,t+300 us); command_seq(4) :=(all_dev ,done ,0,0,0 ns); WHEN OTHERS => NULL; END CASE; ----------------------------------- --10 BIT ADDRESSING, bus is free -- TCs 10 - 15 ----------------------------------- WHEN 10 => -- WRITE TO SLAVE, 10 bit addressing CASE Testcase IS WHEN 1 => -- bus is free, 10 bit addressing, -- write to slave -- master terminates write REPORT "10 bit addressing, write to slave, master terminates write"; command_seq(1) :=(dev0 ,req_bus ,2#1111_0110#,0,0 ns); command_seq(2) :=(dev0 ,write ,slv2,0,0 ns); command_seq(3) :=(dev0 ,write ,2#1010_1110#,0,0 ns); command_seq(4) :=(all_dev ,idle ,0,0,t+300 us); command_seq(5) :=(all_dev ,done ,0,0,0 ns); WHEN 2 => -- bus is free, 10 bit addressing, -- write to slave -- slave terminates write REPORT "10 bit addressing, write to slave, slave terminates write"; command_seq(1) :=(dev0 ,req_bus ,2#1111_0110#,0,0 ns); command_seq(2) :=(dev0 ,write ,slv2,0,0 ns); command_seq(3) :=(dev0 ,write ,16#AA#,0,0 ns); command_seq(4) :=(dev0 ,write ,16#BA#,0,0 ns); command_seq(5) :=(dev0 ,write ,16#BA#,0,0 ns); command_seq(6) :=(dev2 ,idle ,0,0,t+150 us); command_seq(7) :=(dev2 ,dis_sl_resp ,0,0,50 us); command_seq(8) :=(all_dev ,idle ,0,0,t+300 us); command_seq(9) :=(all_dev ,done ,0,0,0 ns); WHEN OTHERS => NULL; END CASE; WHEN 11 => --READ FROM SLAVE, 10 bit addressing CASE Testcase IS WHEN 1 => -- bus is free, 10 bit addressing, -- read from same slave REPORT "10 bit addressing, read from slave"; command_seq(1) :=(dev0 ,req_bus ,2#1111_0110#,0,0 ns); command_seq(2) :=(dev0 ,write ,slv2,0,0 ns); -- restart for read command_seq(3) :=(dev0 ,req_bus ,2#1111_0111#,0,0 ns); command_seq(4) :=(dev0 ,read ,0,4,0 ns); command_seq(5) :=(all_dev ,idle ,0,0,t+600 us); command_seq(6) :=(all_dev ,done ,0,0,0 ns); WHEN OTHERS => NULL; END CASE; WHEN 12 => -- COMBINED FORMAT, first is WRITE, 10 bit addressing CASE Testcase IS WHEN 1 => -- bus is free, 10 bit addressing, -- write to slave -- read from same slave REPORT "10 bit addressing, write to slave, read from same slave"; command_seq(1) :=(dev0 ,req_bus ,2#1111_0110#,0,0 ns); command_seq(2) :=(dev0 ,write ,slv2,0,0 ns); command_seq(3) :=(dev0 ,write ,2#1010_1110#,0,0 ns); -- restart for read command_seq(4) :=(dev0 ,req_bus ,2#1111_0111#,0,0 ns); command_seq(5) :=(dev0 ,read ,0,4,0 ns); command_seq(6) :=(all_dev ,idle ,0,0,t+700 us); command_seq(7) :=(all_dev ,done ,0,0,0 ns); WHEN 2 => -- bus is free, 10 bit addressing, -- write to slave -- repeat write request for same slave REPORT "10 bit addressing, write to slave, restart, write to same slave"; command_seq(1) :=(dev0 ,req_bus ,2#1111_0110#,0,0 ns); command_seq(2) :=(dev0 ,write ,slv2,0,0 ns); command_seq(3) :=(dev0 ,write ,2#1010_1110#,0,0 ns); -- restart for write to same slave command_seq(4) :=(dev0 ,req_bus ,2#1111_0110#,0,0 ns); command_seq(5) :=(dev0 ,write ,slv2,0,0 ns); command_seq(6) :=(dev0 ,write ,2#0010_1111#,0,0 ns); command_seq(7) :=(all_dev ,idle ,0,0,t+500 us); command_seq(8) :=(all_dev ,done ,0,0,0 ns); WHEN 3 => -- bus is free, 10 bit addressing, -- write to slave -- repeat write request for another slave REPORT "10 bit addressing, write to slave, restart, write to another slave"; command_seq(1) :=(dev0 ,req_bus ,2#1111_0110#,0,0 ns); command_seq(2) :=(dev0 ,write ,slv2,0,0 ns); command_seq(3) :=(dev0 ,write ,2#1010_1110#,0,0 ns); -- restart for write to another slave command_seq(4) :=(dev0 ,req_bus ,2#1111_0100#,0,0 ns); command_seq(5) :=(dev0 ,write ,slv3,0,0 ns); command_seq(6) :=(dev0 ,write ,2#0010_1111#,0,0 ns); command_seq(7) :=(all_dev ,idle ,0,0,t+500 us); command_seq(8) :=(all_dev ,done ,0,0,0 ns); WHEN 4 => -- bus is free, 10 bit addressing, -- write to slave -- repeat write request for another slave - 7 bit addressing REPORT "10 bit addressing, write to slave, restart, write to another 7-bit slave"; command_seq(1) :=(dev0 ,req_bus ,2#1111_0110#,0,0 ns); command_seq(2) :=(dev0 ,write ,slv2,0,0 ns); command_seq(3) :=(dev0 ,write ,2#1010_1110#,0,0 ns); -- restart for write to another slave command_seq(4) :=(dev0 ,req_bus ,slv1_w,0,0 ns); command_seq(5) :=(dev0 ,write ,slv3,0,0 ns); command_seq(6) :=(dev0 ,write ,2#0010_1111#,0,0 ns); command_seq(7) :=(all_dev ,idle ,0,0,t+500 us); command_seq(8) :=(all_dev ,done ,0,0,0 ns); WHEN 5 => -- bus is free, 10 bit addressing, -- write to slave -- repeat read request for another slave - 7 bit addressing REPORT "10 bit addressing, write to slave, restart, read from another 7-bit slave"; command_seq(1) :=(dev0 ,req_bus ,2#1111_0110#,0,0 ns); command_seq(2) :=(dev0 ,write ,slv2,0,0 ns); command_seq(3) :=(dev0 ,write ,2#1010_1110#,0,0 ns); -- restart for read to another slave command_seq(4) :=(dev0 ,req_bus ,slv1_r,0,0 ns); command_seq(5) :=(dev0 ,read ,0,2,0 ns); command_seq(6) :=(all_dev ,idle ,0,0,t+500 us); command_seq(7) :=(all_dev ,done ,0,0,0 ns); WHEN OTHERS => NULL; END CASE; WHEN 13 =>-- COMBINED FORMAT, first is READ, 10 bit addressing CASE Testcase IS WHEN 1 => -- bus is free, 10 bit addressing, -- read from slave, restart, read form same slave REPORT "10 bit addressing, read from slave, restart, read from same slave"; command_seq(1) :=(dev0 ,req_bus ,2#1111_0110#,0,0 ns); command_seq(2) :=(dev0 ,write ,slv2,0,0 ns); -- restart for read command_seq(3) :=(dev0 ,req_bus ,2#1111_0111#,0,0 ns); command_seq(4) :=(dev0 ,read ,0,4,0 ns); command_seq(5) :=(dev0 ,req_bus ,2#1111_0111#,0,0 ns); command_seq(6) :=(dev0 ,read ,0,4,0 ns); command_seq(7) :=(all_dev ,idle ,0,0,t+1100 us); command_seq(8) :=(all_dev ,done ,0,0,0 ns); WHEN 2 => -- bus is free, 10 bit addressing, -- read from slave, write to same slave REPORT "10 bit addressing, read from slave, write to same slave"; command_seq(1) :=(dev0 ,req_bus ,2#1111_0110#,0,0 ns); command_seq(2) :=(dev0 ,write ,slv2,0,0 ns); -- restart for read command_seq(3) :=(dev0 ,req_bus ,2#1111_0111#,0,0 ns); command_seq(4) :=(dev0 ,read ,0,3,0 ns); -- restart write to slave4 command_seq(5) :=(dev0 ,req_bus ,2#1111_0110#,0,0 ns); command_seq(6) :=(dev0 ,write ,slv2,0,0 ns); command_seq(7) :=(all_dev ,idle ,0,0,t+1000 us); command_seq(8) :=(all_dev ,done ,0,0,0 ns); WHEN 3 => -- bus is free, 10 bit addressing, -- read from slave, write to another slave REPORT "10 bit addressing, read from slave, write to another slave"; command_seq(1) :=(dev0 ,req_bus ,2#1111_0110#,0,0 ns); command_seq(2) :=(dev0 ,write ,slv2,0,0 ns); -- restart for read command_seq(3) :=(dev0 ,req_bus ,2#1111_0111#,0,0 ns); command_seq(4) :=(dev0 ,read ,0,4,0 ns); -- restart write to slave4 command_seq(5) :=(dev0 ,req_bus ,2#1111_0100#,0,0 ns); command_seq(6) :=(dev0 ,write ,slv3,0,0 ns); command_seq(7) :=(all_dev ,idle ,0,0,t+800 us); command_seq(8) :=(all_dev ,done ,0,0,0 ns); WHEN 4 => -- bus is free, 10 bit addressing, -- read from slave -- repeat write request for another slave - 7 bit addressing REPORT "10 bit addressing, read from slave, write to another 7-bit slave"; command_seq(1) :=(dev0 ,req_bus ,2#1111_0110#,0,0 ns); command_seq(2) :=(dev0 ,write ,slv2,0,0 ns); -- restart for read command_seq(3) :=(dev0 ,req_bus ,2#1111_0111#,0,0 ns); command_seq(4) :=(dev0 ,read ,0,4,0 ns); -- restart write to slv2 command_seq(5) :=(dev0 ,req_bus ,slv1_w,0,0 ns); command_seq(6) :=(dev0 ,write ,slv3,0,0 ns); command_seq(7) :=(dev0 ,write ,2#0010_1111#,0,0 ns); command_seq(8) :=(all_dev ,idle ,0,0,t+800 us); command_seq(9) :=(all_dev ,done ,0,0,0 ns); WHEN 5 => -- bus is free, 10 bit addressing, -- read from slave -- repeat read request for another slave - 7 bit addressing REPORT "10 bit addressing, read from slave, read from another 7-bit slave"; command_seq(1) :=(dev0 ,req_bus ,2#1111_0110#,0,0 ns); command_seq(2) :=(dev0 ,write ,slv2,0,0 ns); -- restart for read command_seq(3) :=(dev0 ,req_bus ,2#1111_0111#,0,0 ns); command_seq(4) :=(dev0 ,read ,0,4,0 ns); -- restart to read from slv2 command_seq(5) :=(dev0 ,req_bus ,slv1_r,0,0 ns); command_seq(6) :=(dev0 ,read ,0,2,0 ns); command_seq(7) :=(all_dev ,idle ,0,0,t+800 us); command_seq(8) :=(all_dev ,done ,0,0,0 ns); WHEN OTHERS => null; END CASE; WHEN 14 =>-- COMBINED FORMAT, NEGATIVE, CASE Testcase IS WHEN 1 => -- bus is free, 10 bit addressing, -- read from slave, restart, try to read from another slave REPORT "Negative, 10 bit addressing, read from slave, restart, read from another slave"; command_seq(1) :=(dev0 ,req_bus ,2#1111_0110#,0,0 ns); command_seq(2) :=(dev0 ,write ,slv2,0,0 ns); -- restart for read command_seq(3) :=(dev0 ,req_bus ,2#1111_0111#,0,0 ns); command_seq(4) :=(dev0 ,read ,0,4,0 ns); command_seq(5) :=(dev0 ,req_bus ,2#1111_0101#,0,0 ns); command_seq(6) :=(all_dev ,idle ,0,0,t+600 us); command_seq(7) :=(all_dev ,done ,0,0,0 ns); WHEN 2 => -- bus is free, 10 bit addressing, -- write to slave,restart, try to read from another slave REPORT "NEGATIVE, 10 bit addressing, write to slave, read from another slave"; command_seq(1) :=(dev0 ,req_bus ,2#1111_0110#,0,0 ns); command_seq(2) :=(dev0 ,write ,slv2,0,0 ns); command_seq(3) :=(dev0 ,write ,2#1010_1110#,0,0 ns); -- restart for read from not addressed slave command_seq(4) :=(dev0 ,req_bus ,2#1111_0101#,0,0 ns); command_seq(5) :=(all_dev ,idle ,0,0,t+500 us); command_seq(6) :=(all_dev ,done ,0,0,0 ns); WHEN OTHERS => null; END CASE; WHEN 15 => -- NO RESPONSE, NEGATIVE -- initial byte only -- no response CASE Testcase IS WHEN 1 => -- bus is free -- 10 bit addressing, -- master address 1111_0000, no response REPORT "Negative, 10 bit addressing, no response"; command_seq(1) :=(dev0 ,req_bus ,2#1111_0000#,0,0 ns); command_seq(2) :=(all_dev ,idle ,0,0,t+300 us); command_seq(3) :=(all_dev ,done ,0,0,0 ns); WHEN 2 => -- bus is free -- 10 bit addressing, -- addressed slave is unabble to response REPORT "Negative, 10 bit addressing, slave is not enabled to response"; command_seq(1) :=(dev0 ,req_bus ,2#1111_0110#,0,0 ns); command_seq(2) :=(dev0 ,write ,slv2,0,0 ns); command_seq(3) :=(dev2 ,idle ,0,0,t_curr+150 us); command_seq(4) :=(dev2 ,dis_sl_resp ,0,0,50 us); command_seq(5) :=(all_dev ,idle ,0,0,t+300 us); command_seq(6) :=(all_dev ,done ,0,0,0 ns); WHEN 3 => -- bus is free -- 10 bit addressing, -- addressed slave is unabble to response REPORT "Negative, 10 bit addressing, slave is not enabled to response for read"; command_seq(1) :=(dev0 ,req_bus ,2#1111_0110#,0,0 ns); command_seq(2) :=(dev0 ,write ,slv2,0,0 ns); -- restart for read command_seq(3) :=(dev0 ,req_bus ,2#1111_0111#,0,0 ns); command_seq(4) :=(dev2 ,idle ,0,0,t_curr+200 us); command_seq(5) :=(dev2 ,dis_sl_resp ,0,0,50 us); command_seq(6) :=(all_dev ,idle ,0,0,t+300 us); WHEN 4 => -- bus is free, invalid 10 bit addressing, r/w bit is 1 REPORT "Negative, invalid 10 bit addressing, r/w bit is 1"; command_seq(1) :=(dev0 ,req_bus ,2#1111_0111#,0,0 ns); command_seq(2) :=(all_dev ,idle ,0,0,t+300 us); command_seq(3) :=(all_dev ,done ,0,0,0 ns); WHEN OTHERS => NULL; END CASE; WHEN 16 => -- START BYTE CASE Testcase IS WHEN 1 => REPORT "Master writes start byte, writes data to slv1"; -- no device is allowed to ACK command_seq(1) :=(dev0 ,req_bus ,start,0,0 ns); command_seq(2) :=(dev0 ,req_bus ,slv1_w,0,0 ns); command_seq(3) :=(dev0 ,write ,0,0,0 ns); command_seq(4) :=(all_dev ,idle ,0,0,t+300 us); command_seq(5) :=(all_dev ,done ,0,0,0 ns); WHEN OTHERS => NULL; END CASE; WHEN 20 => -- LOSE ARBITRATION CASE Testcase IS WHEN 1 => REPORT "Lose arbitration "; command_seq(1) :=(dev0 ,req_bus ,2#1111_0110#,0,0 ns); command_seq(2) :=(dev0 ,write ,slv2,0,0 ns); command_seq(3) :=(dev0 ,write ,slv2,0,0 ns); command_seq(4) :=(dev1 ,req_bus ,gen_call,0,0 ns); command_seq(5) :=(dev1 ,write ,2#1111_0000#,0,0 ns); command_seq(6) :=(all_dev ,idle ,0,0,t+300 us); command_seq(7) :=(all_dev ,done ,0,0,0 ns); WHEN 2 => REPORT "Lose arbitration "; command_seq(1) :=(dev0 ,req_bus ,2#1111_0110#,0,0 ns); command_seq(2) :=(dev0 ,write ,slv2,0,0 ns); command_seq(3) :=(dev0 ,write ,slv2,0,0 ns); command_seq(4) :=(dev1 ,req_bus ,2#1111_0110#,0,0 ns); command_seq(5) :=(dev1 ,write ,2#1111_0000#,0,0 ns); command_seq(6) :=(all_dev ,idle ,0,0,t+300 us); command_seq(7) :=(all_dev ,done ,0,0,0 ns); WHEN OTHERS => NULL; END CASE; WHEN OTHERS => null; END CASE; IF device_id = dev0 THEN REPORT "------------------------------------------------------"; END IF; END PROCEDURE Generate_TC; END PACKAGE BODY i2c_drive_ms_pkg;